2.Code design, simulation, system constraints, white box testing
代码设计，仿真，系统约束，白盒测试
3.Code review, Joint debugging
设计代码审核，联合调试等
2.3year+ experience in FPGA design experience, familiar with VHDL/ Verilog /SystemVerilog
3年以上逻辑开发经验，熟悉VHDL ,Verilog or SystemVerilog 硬件描述语言
3.Familiar with Xilinx/Intel architecture and have relevant development experience
熟悉Xilinx ,Intel芯片架构，具有相关开发经验
4.Master FPGA verification methods, Vunit / UVM experience is preferred
掌握FPGA验证方法，有Vunit/UVM 经验者更佳
5.Master Place & Route, timing knowledge
精通布局、布线，时序分析和时序约束
6.Familiar with Ethernet, CPRI protocol, TCL/Python script
熟悉以太网, CPRI 协议, 熟悉TCL/Python 脚本
7.Common control interfaces design (e.g. AMBA AXI, DDR, Highspeed SerDes.)
有通用接口设计经验（例如AMBA AXI，DDR, Highspeed SerDes）
8.Good English verbal communication skill, fluent in reading and writing skill
英语口语较好，具备流利读写的能力
Preferred (as a plus)
青睐要求
1.Radio Design or Verification experience
具有无线通信（Radio）的相关设计验证经验
2.Broader knowledge of Telecom, ICT, Automotive and other industries
具有通信、ICT、汽车等行业的知识
